The present invention relates to a semiconductor technology and, more particularly, to a technology which is effected when applied to a semiconductor integrated circuit device having a DRAM (i.e., Dynamic Random Access Memory) and to a technology for forming the former.
A memory cell of the DRAM for latching an information of 1 [bit] is constructed of a series circuit between a memory cell selecting MISFET and a information storing capacity element. The memory cell selecting MISFET of the aforementioned memory cell is formed over the principal surface of the active regions of a semiconductor substrate (or well regions). The active regions of the semiconductor substrate are formed within the region which are surrounded by an element separating insulating film (i.e., a field insulating film) formed in the inactive regions of the aforementioned semiconductor substrate and channel stopper regions. The aforementioned memory cell selecting MISFET has its gate electrodes connected with word lines extending in a row direction. One of the semiconductor regions of the memory cell selecting MISFET are connected with complementary data lines. The other semiconductor regions are connected with one of the electrode of the aforementioned information storing capacity element. This information storing capacity element has its other electrode supplied with a predetermined potential.
The DRAM of this kind has a tendency of being integrated to have a larger capacity and having its memory cells small-sized. In case the size of the memory cells is reduced, the size of the information storing capacity element is also reduced so that the amount of charge storage or information is dropped. This reduction in the charge storage will drop the α-ray soft error withstand voltage. Therefore, it is an important technical target of the DRAM having a capacity as large as 1 [Mbit] or more to improve the α-ray soft error withstand voltage.
On the basis of this technical target, there is a tendency that the stacked structure (i.e,. STC structure) is adopted in the information storing capacity element of the memory cell of the DRAM. The information storing capacity element of this stacked structure is constructed by laminating a lower electrode layer, a dielectric film and an upper electrode layer sequentially. The lower electrode layer is partially connected with other semiconductor region of the memory cell selecting MISFET and has its other portion extended to over the gate electrodes. The upper electrode layer is formed over the aforementioned lower electrode layer through a dielectric film. This upper electrode layer is integrated with the upper electrode layer of the information storing capacity element of the stacked structure of another adjoining memory cell so that it may be used as a common plate electrode.
Incidentally, the DRAM acting as the information storing capacity element of the stacked structure and constructing the memory cell is disclosed in U.S. application Ser. No. 07/246,514 filed on Sep. 19, 1988, for example.